Opto-electronic devices such as lasers, optical amplifiers and modulators are commonly made using one or more p-n junctions that are formed when differently doped semiconductor materials are located against each other.
Dopants are materials typically introduced into semiconductor materials to bond within the semiconductor lattice. Once bonded into the semiconductor lattice, dopant atoms typically donate either an electron or a hole to the crystal lattice, depending on the type of dopant used. The donated electron or hole is free to move about the semiconductor lattice and becomes a conducting charge carrier. Semiconductor materials that have been doped to have an excess of electron charge carriers are called n-type semiconductors, whilst semiconductors that have been doped to have an excess of holes are called p-type semiconductors. These materials shall be termed ‘n-type’ and ‘p-type’ hereinafter throughout the application.
When an n-type and a p-type are located adjacent to each other, the resulting interface between the materials becomes a p-n junction. The basic p-n junction is the interface between two semiconductor materials wherein a depletion region exists about the junction with nominally no free (conduction) charge carriers because the holes at the junction material migrate away towards the p-type material whilst the electrons at the junction migrate away towards the n-type material. The resulting imbalance of charge carrier type either side of the p-n junction gives rise to a potential difference across the junction that is commonly exploited in many electronic and optoelectronic devices. This inherent potential difference is often exploited as a threshold value that a voltage applied across the junction must overcome in order for current to flow across the junction. When a drive voltage is applied to cause the electrons in the n-type and holes in the p-type to flow towards the p-n junction, this is known as ‘forward bias’. When a drive voltage is applied to cause the electrons in the n-type and holes in the p-type to flow away from the p-n junction, this is known as ‘reverse bias’.
When electrons and holes combine in a direct band gap semiconductor material, the electrons lose energy and turn from conduction electrons to valence electrons and in the process can emit light at a particular wavelength depending on the band gap between the valence and conduction bands in the semiconductor material. Conversely if light is incident upon the p-n junction with an energy (hence wavelength) that can be absorbed by the semiconductor material, electrons and holes are created in the p-n junction.
Optoelectronic devices such as semiconductor optical amplifiers and lasers exploit the p-n junction by applying forward bias to the junction causing the electrons and holes to meet in the depletion region and combine. The recombination at the p-n junction produces light that can be harnessed in a number of ways, for example: producing an incoherent light source when the opto-electronic device is an LED, a coherent light source if the opto-electronic device is a laser or for optical amplification when the opto-electronic device is a semiconductor optical amplifier (SOA).
Optoelectronic devices such as photodetectors and electro-absorption modulators exploit the p-n junction by applying reverse bias to the junction. When light is incident on the p-n junction of a photodetector and is absorbed by the semiconductor material, conduction holes and electrons are created that correspondingly get driven from the depletion region generating photocurrent. Electro-absorption modulators apply varying amounts of reverse bias to dynamically change the bandgap of the semiconductor, thus modulating the amount of light absorbed in the depletion region at a particular wavelength.
It is often desirable to make opto-electronic devices such as lasers, modulators and amplifiers that can be turned on or off at high speeds. This is important in optical communications where high bit rates are often required. One of the main properties of an opto-electonic device that limits the speed of operation is the capacitance across the p-n junction. The lower the capacitance, the higher the speed of the device.
Opto-electronic devices are typically formed using a variety of deposition and lithographic methods. Semiconductor devices commonly use the deposition method MOVPE (Metal Organic Vapour Phase Epitaxy)
When a semiconductor device is formed, it is known to use one or more different semiconductor materials. Typical semiconductor materials used for opto-electronic devices include indium phosphide (InP) and gallium arsenide (GaAs). If the p-type and n-type materials are differently doped versions of the same semiconductor material then the p-n junction is called a homo junction. If however semiconductor materials of the junction are different (apart from being doped differently) then the p-n junction is called a heterojunction. Heterojunctions can be alternatively formed by sandwiching one or more different undoped (intrinsic) semiconductor layers between n-type and p-type layers whereby the sandwiched layer or layers is known as an active layer or stack. The active layer/s or stack is a typically chosen for its optical properties and may be arranged to act as a single or a stack of quantum wells that act as optical waveguides confining the light.
It is also known to lithographically define the one or more p-n junctions as an upstanding ‘mesa’ and then surround the mesa using one or more ‘re-growth’ steps with other materials, for example other semiconductors, so that the junction is ‘buried’ within the device. Burying the mesa results in a lower refractive index contrast to the side of the active waveguide than if air was disposed to the side of the active waveguide. This lower refractive index contrast makes the waveguide less prone to waveguide sidewall scattering loss. Furthermore, burying the active layer gives a larger top surface area to form an electrical contact on that helps reduce contact resistance. The surrounding layers are often semiconductor materials deposited using one of the above-mentioned deposition techniques. FIG. 1 shows a cross section of a laser of the prior art where semiconductor material is deposited around the sides of a buried heterojunction. In order to optimise the efficiency of an optoelectronic device such as a laser, it is desirable for current to be directed only through the active layer and not through the surrounding materials layers. When current flows through the surrounding layers adjacent to the active layer, this is known as ‘leakage current’. Reverse biased current blocking junctions
One method of the prior art that helps prevent ‘leakage’ current flowing through the surrounding semiconductor layers involves forming one or more ‘current blocking’ junctions (or structures) either side of the active device. The current blocking junction is typically a p-n junction formed using differently doped semiconductor layers and is designed to act as a reverse bias junction when the heterojunction with the active layer is in forward bias. A cross section of a laser device of the prior art with a current blocking junction is shown in FIG. 1 whereby the active layer 3 of the device is above n-type InP buffer layer 2 and substrate 1 and below the p-type InP layers 4 and 7 thus creating a heterojunction. Immediately to either side of the active layer is a p-type layer 5 below an n-type layer 6. Above layer 7 is a p type contact 8, a masking layer 9 and a metal contact 10. Because the orientation of p-n layers 5 and 6 are reversed in the vertical direction to layers 4 and 2, the current blocking junction is in a reverse bias configuration to the heterojunction. By having reversed biased ‘current blocking’ junctions either side of a forward biased junction with an active layer, electrons and holes are funneled into the active layer increasing the efficiency of the opto-electronic device.
One problem with conventional current blocking structures is that reverse biased p-n current blocking junctions suffer from a problem called thyristor action which at high drive currents and/or temperatures can result in the blocking structure breaking down and allowing a large current flow to pass through the current locking structure and away from the active layer/s, thus reducing the efficiency of the device.
It is has been recognised, (for example in “Analysis of current leakage in InGaAsP/InP buried heterostructure” Ohtoshi, T. et al. Journal of Quantum Electronics, Vol. 25, no. 6, pages 1369-1375), that to get low leakage current reverse biased junctions the thickness and doping levels of the blocking layers must be increased.
Despite these limitations, reverse biased p-n current blocking layers remain the standard method of limiting leakage current in devices that only require electrical modulation at moderate bit rates of up to approximately 1 Gbit/s.
Reverse biased p-n current blocking layers are also not ideally suited to higher bit rate modulation due to the large parasitic capacitance that the reverse biased junction causes within the device. Patent document EP1300917 (Ryder, et al) discloses an optoelectronic device incorporating a graded p-doped layer below the current blocking structure to reduce the device capacitance, however this structure is still subject to thyristor action at high temperatures and drive currents.
Semi-Insulating Layers
One approach to reduce device capacitance has been to replace the said reverse biased p-n junction blocking layers with one or more semiconductor layers that provide a higher resistivity than the surrounding semiconductor layers. Such high resistivity layers are often termed semi-insulating semiconductors and appear essentially undoped when measured using Capacitance Voltage (CV) profiling. Semi-insulating semiconductors provide current blocking without the large capacitance of a reverse biased current blocking junction.
Semiconductors may be doped using specific dopants that act to ‘trap’ conduction electrons and holes (otherwise known as electron or hole traps) for later release by thermal emission. The effect of these traps reduces the amount of conduction electrons flowing though the trapping region, thus making the ‘trap-doped’ semiconductor material semi-insulating.
Semi-insulating doped current blocking layers have previously been formed by replacing the layers 5 and 6 in FIG. 1 with iron (Fe) doped indium phosphide (InP) wherein the Fe dopant atoms act as electron traps. However, in semiconductor lasers and optical amplifiers where the device needs to operate under forward bias, Fe doped lasers are typically found to suffer from higher current leakage than conventional reverse biased p-n junction current blocking layers. One known cause of this excess leakage is the inter-diffusion of Fe with the commonly used p-type InP dopants such as Zinc (Zn).
Wasserbauer in conference paper TuB.4 from IPRM (Indium Phosphide and Related Materials Conference) in 1990 also showed that the resistivity of Fe doped InP is highly temperature dependant with the leakage current increasing by around 1 order of magnitude as the temperature was increased by every 25° C. above room temperature. This increased current leakage at higher device temperatures causes leakage problems when using Fe doped InP in uncooled semiconductor devices which need to operate at chip temperatures of up to 95° C.
Patent document WO 95/02910 discloses a number of semi-insulating dopants that act as hole traps such as Cr or Ti that can be used to form low capacitance current blocking layers when the hole trapping material is surrounded by p doped InP.
Ru—InP Layers
Ruthenium (Ru) doped semiconductors have previously been used as a low capacitance current blocking layer for both forward and reverse biased devices. Ru-doped InP has been shown in the prior art to be an effective hole trap but a poor electron trap. The interest in the material has resulted from the fact that Ru does not suffer from inter-diffusion problems with Zn or other commonly used p-type dopants.
U.S. Pat. No. 6,815,786 describes blocking layers grown around a mesa with an active layer. FIG. 2 show a diagrammatic representation of the device described in this patent document. A first thin layer of Fe doped InP 11 is grown adjacent to the mesa, followed by a thick layer 12 of Ru doped InP where said Ru doped layer is grown in a manner that makes it semi-insulating to enable a low device capacitance to be achieved.
U.S. Pat. No. 6,717,187 describes a structure similar to that described in U.S. Pat. No. 6,815,786 and shown in FIG. 2 but where the material used for layer 11 is the Ru—InP and layer 12 is Fe—InP, such that the Ru doped InP layer is adjacent to the mesa side wall, while the thicker Fe doped layer is located above the Ru layer. In the structure described in U.S. Pat. No. 6,717,187, the Ru layer is made to be semi-insulating so that current does not pass vertically through the Ru—InP layer and into the active region 3 that it contacts. The semi-insulating Ru—InP layer in this patent document is used to block the inter-diffusion of the Zn from mesa layer 7 and the Fe from layer 12.
Patent document DE19747996C1 discloses that in order to grow Ru in a form that is semi-insulating it is necessary to use processing conditions that can undesirably lead to the formation of growth defects referred to as hillocks. Hillocks cause growth morphology problems that reduce the yield of devices in a processing run. When grown as a semi-insulating current blocking layer only thin Ru-doped layers can be used if good morphology is to be maintained.
The Conference paper MoA2.4 by Lealman et al, shown at IPRM (Indium Phosphide and Related Materials Conference) May 2008 together with its corresponding presentation describes a current blocking structure with a single layer of Ru doped InP sandwiched in between single layers of (p-type) Zn InP as shown in FIG. 3. The ‘p-Ru-p’ current blocking structure was fabricated using atmospheric pressure MOVPE that focused on using Ru precursors of bis-isopropylcycopentadienyl ruthernium (IPCPRU) and bis-isobutylcycopentadienyl ruthenium (IBCPRu). The paper disclosed that the Ru—InP layer made using this method acted as a semiconductor layer with a low n-type doping and that the p-Ru-p structure showed capacitances higher than a normal standard p-n junction blocking structure. The 1st re-growth step around the mesa was composed of a thin 0.1 μm Zn doped InP layer 5, followed by a thick 0.8 μm layer of Ru doped InP 17 followed and capped with another thin 0.1 μm layer of Zn doped InP 18.
In contrast to U.S. Pat. No. 6,717,187 and U.S. Pat. No. 6,815,786 where the Ru—InP layers were grown to be semi-insulating and block the diffusion of Fe, conference paper MoA2.4 grew the Ru—InP as a low n-type layer so that it could form part of a reverse bias p-n junction current blocking structure wherein the Ru—InP still exhibited higher resistivity than conventional p-n junctions.
Because the Ru—InP layer was only low n-type doped, the Ru—InP blocking layer was grown to a large thickness of 0.8 μm in comparison to the thickness of the p-type layers in the blocking junction which were only grown to a thickness of 0.1 μm. When the Ru—InP layer in MoA2.4 was thinned to 0.6 μm thickness, a further 0.3 μm layer of semi-insulating Fe-doped InP was introduced below the Ru—InP. The problem with the increased thickness of the Ru—InP in the p-Ru-p structure was that the device showed higher capacitances than a normal standard p-n junction blocking structure and thus was not be suitable for operation at 1 OGbit/s modulation rates. Furthermore, thick layers of Ru—InP still suffer from morphology problems and are difficult to grow.